Channel Parameters

BASELINE_AVERAGE

The module measures baselines continuously and effectively extracts DC-offsets from these measurements. The DC-offset value is needed to apply a correction to the computed energies. To reduce the noise contribution from this correction baseline samples are averaged in a geometric weight scheme. The averaging depends on LOG2BWEIGHT:

DC_avg = DC_avg + (DC - DC_avg) 2^LOG2BWEIGHT

DC is the latest measurement and DC_avg is the average that is continuously being updated. At the beginning, and at the resuming, of a run, DC_avg is seeded with the first available DC measurement. As before, the DSP ensures that LOG2BWEIGHT will be negative. The noise contribution from the DC-offset correction falls with increased averaging. The standard deviation of DC_avg falls in proportion to √(2^LOG2BWEIGHT).

When using a BLCUT value from a noise measurement the module will internally adjust the effective LOG2BWEIGHT for best energy resolution, up to the maximum value given by LOG2BWEIGHT. Hence, the Log2Bweight setting should be chosen at low count rates (dead time < 10%). Best energy resolutions are typically obtained at values of -3 to -4, and this parameter does not need to be adjusted afterwards.

BASELINE_PERCENT

This variable sets the DC-offset level in terms of the percentage of the ADC range. The DSP uses this variable to set the DC-offset level when it is executing the Pixie16AdjustOffsets().

BINFACTOR

Controls the binning of the histogram. Energy values are calculated to 16 bits precision. The LSB corresponds to 1/16th of a 12-bit ADC. The PIXIEs, however, do not have enough histogram memory available to record 64K spectra, nor would this always be desirable. The user is therefore free to control the binning. Observe the following formula to find to which MCA bin a value of Energy will contribute:

MCAbin = Energy 2Log2Ebin

As can be seen, Log2Ebin should be a negative number to achieve the correct behaviour. At run start the DSP program ensures that Log2Ebin is indeed negative by replacing the stored value by -abs(Log2Ebin).

This parameter can take values of [1, 16] in integer steps.

BLCUT

This variable sets the cutoff value in ADC units for baselines in baseline measurements. If BLCUT is not set to zero, the DSP checks continuously each baseline value to see if it is outside the limit set by BLCUT. If the baseline value is within the limit, it will be used to calculate the average baseline value. Otherwise, it will be discarded. Set BLCUT to zero to not check baselines, therefore reduce processing time.

Pixie16AcquireBaselines() can be used to measure baselines. You can then histogram these baseline values and determine the appropriate value for BLCUT for each channel according to the standard deviation SIGMA for the averaged baseline value. BLCUT could be set to be three times SIGMA.

CFDDelay

This variable defines the delay in microseconds for the CFD calculation. The CFD algorithm builds the difference of original and delayed/scaled ADC signal. See user manual for details.

CFDScale

This variable defines the CFD scaling factor. The CFD algorithm builds the difference of original and delayed/scaled ADC signal. See user manual for details.

CFDThresh

This sets the threshold in ADC units of the constant fraction discriminator (CFD) trigger that is implemented in the trigger/filter FPGA.

CHANNEL_CSRA

The control and status register bits controlling various aspects of the module operation.

Bit	Description
0	Fast trigger selection. 1: select external fast trigger. 0: select local fast trigger
1	Module validation signal selection. 1: select module gate signal. 0: select global validation signal
2	Good channel. Only channels marked as good will contribute to spectra and list mode data.
3	Channel validation signal selection. 1: select channel gate signal. 0: select channel validation signal
4	Block data acquisition if trace or header DPMs are full. 1: enable. 0: disable.
5	Trigger positive. Set this bit to trigger on a positive slope; clear it for triggering on a negative slope. The trigger/filter FPGA can only handle positive signals. The Pixie-16 handles negative signals by inverting them immediately after entering the FPGA.
6	Veto channel trigger. 1: enable. 0: disable.
7	Not implemented.
8	Enable trace capture. Set to 1 to enable trace capture for this channel. Set to 0 to disable trace capture.
9	Enable QDC sums capture. Set to 1 to enable QDC sums capture for this channel. Set to 0 to disable QDC sums capture.
10	Enable CFD trigger mode. Set to 1 to enable CFD trigger mode for this channel. Set to 0 to disable CFD trigger.
11	Enable the requirement for module validation trigger. Set to 1 to require module validation trigger for events validation for this channel. Set to 0 to disable the requirement for module validation trigger.
12	Enable capture raw energy sums and baselines. Set to 1 to store raw energy sums and baselines for events captured in this channel. Set to 0 to not capture raw energy sums and baselines.
13	Enable the requirement for channel validation trigger. Set to 1 to require channel validation trigger for events validation for this channel. Set to 0 to disable the requirement for channel validation trigger.
14	Enable input relay. This bit controls the ON or OFF position switching of the input relay of each channel of the Pixie-16, resulting in two discrete fixed gains for the input signal: one high and one low. The actual gain value depends on the input design of each particular Pixie-16 hardware variant.
15-16	Pileup rejection control. [0,0] record all events (trace, timestamps, etc., but no energy for piled-up events) | [0,1] reject pile-up events | [1,0] record trace, timestamps, etc. for piled-up events but do not record trace for single events | [1,1] record record trace, timestamp, energy for piled-up events only
17	Enable “no trace for large pulses” feature. 1: enable. 0: disable.
18	Group trigger selection. 1: external group trigger. 0: local fast trigger.
19	Channel veto selection. 1: channel validation trigger. 0: front panel channel veto.
20	Module veto selection. 1: module validation trigger. 0: front panel module veto.
21	External timestamps in event header. 1: enable; 0: disable.
22-31	Reserved

CHANNEL_CSRB

Warning

Not implemented

ChanTrigStretch

The channel validation trigger from the system FPGA is extended by this value in microseconds. See Section 3.3.10 in the user manual.

EMIN

An energy cutoff value which is used to determine whether to record trace in list mode data runs, i.e. the “no trace for large pulses” feature: 1) if the computed energy is above EnergyLow (or EMIN as described in section 4.2.4), trace will not be recorded; 2) if the computed energy is equal to or smaller than EnergyLow, trace will be recorded. This feature is only effective if bit 17 of CHANNEL_CSRA is set to 1. In other words, if bit 17 of ChanCSRA is set to 0, the value of EnergyLow has no effect on trace recording.

ENERGY_FLATTOP

The energy filter flattop. It has a range of [0.024, 63.488] microseconds. The available length can vary depending on the setting of SLOW_FILTER_RANGE.

ENERGY_RISETIME

The energy filter risetime. It has a range of [0.016, 64] microseconds. The available length can vary depending on the setting of SLOW_FILTER_RANGE.

ExternDelayLen

This parameter is used to delay the incoming ADC waveform and the local fast trigger in order to compensate for the delayed arrival of the external trigger pulses, e.g., module validation trigger, channel validation trigger, etc.

ExtTrigStretch

This parameter is used to stretch the module validation trigger pulse. Only relevant when module validation is required by setting CHANNEL_CSRA bit 11 to 1.

FASTTRIGBACKLEN

Length of trigger for coincidence logic in system FPGA in microseconds. See user manual section 3.3.10 for details.

FtrigoutDelay

Delay for sending trigger to system FPGA for coincidence logic in microseconds. See user manual section 3.3.10 for details.

INTEGRATOR

Warning

Not implemented

MultiplicityMaskH

Upper 32-bits of the bit patterns controlling the coincidence logic. See user manual for details.

MultiplicityMaskL

Lower 32-bits of the bit patterns controlling the coincidence logic. See user manual for details.

QDCLen0

Length of the QDC sum 0.

QDCLen1

Length of the QDC sum 1.

QDCLen2

Length of the QDC sum 2.

QDCLen3

Length of the QDC sum 3.

QDCLen4

Length of the QDC sum 4.

QDCLen5

Length of the QDC sum 5.

QDCLen6

Length of the QDC sum 6.

QDCLen7

Length of the QDC sum 7.

RESET_DELAY

Warning

This parameter is not available for all firmware versions. Please refer to your firmware documentation to confirm functionality.

Adjusts the delay between the fast trigger and the CFD zero-crossing point search.

For fast pulses, the fast trigger may arrive earlier than the time when the CFD computation is ready. In this situation, the system generates an erroneous CFD forced trigger and misses the true CFD trigger. The ResetDelay allows users to adjust the delay between the fast trigger and the CFD zero-crossing search on a per channel basis. This ensures that the CFD computation is ready when the fast trigger arms.

TAU

Preamplifier exponential decay time in units of microseconds. The DSP uses this variable to compute coefficients for the event energy calculations. For more information, please refer to High Rate Pulse Processing Algorithms for Microcalorimeters

TRACE_DELAY

The value in microseconds to delay the trigger in the collected ADC trace. This value is only applicable to list-mode data runs.

TRACE_LENGTH

This tells the DSP how many words of trace data to read for each event in units of microseconds. The action taken depends on FIFOlength, whose value depends on hardware variants and specific firmware implementations. If TraceLength < FIFOlength, the DSP will read from the FIFO. In that case individual samples are either 10 ns (100 MHz or 500 MHz modules) or 8 ns (250 MHz) apart. If FIFOlength <= TraceLength, the SDK will force the TraceLength to be equal to FIFOlength.

TRIGGER_FLATTOP

The trigger filter’s flattop. Can take values of [0, 1] microseconds.

TRIGGER_RISETIME

The trigger filter’s rise time. Can take values of [0.016, 1.016] microseconds.

TRIGGER_THRESHOLD

This is the trigger threshold used by the trigger filter to validate a trigger.

VetoStretch

This parameter is used to stretch the veto pulse for this channel in units of microseconds.

VOFFSET

Allows users to set the channel’s voltage offset. It can take values of [-1.5, 1.5] V.

XDT

This parameter controls the number of clock cycles between untriggered ADC traces in Pixie16AcquireADCTrace(). The time between recorded samples is \(\Delta\)T = XWAIT*10ns.